Methodical Low-Power ASIP Design Space Exploration

摘要

Application-specific instruction set processors (ASIPs) are an excellent implementation paradigm for mixed control-/data-flow oriented tasks with medium to low data rate and high complexity. The main advantage of ASIPs is the higher flexibility due to programmability compared to dedicated hardware. This article discusses an ASIP design methodology starting from the instruction set architecture description language LISA, which enables automatic generation of the necessary DSP tools like assembler, linker and simulator as well as generation of large parts of the synthesizable hardware description. The presented methodology has the goal to obtain working silicon in a short amount of time. Furthermore, the classical parameters computational performance and area are jointly considered with the impact of architectural modifications on energy consumption using gate-level estimations. Different pipeline structures from two to four pipeline stages together with several ASIP energy optimization options have been implemented and evaluated. These optimizations include clock-gating, logic netlist restructuring, data-path optimization, instruction memory power reduction by optimized instruction encoding, and implementation of a dedicated coprocessor. The practical applicability of this methodology is demonstrated with the ICORE ASIP for DVB-T acquisition and tracking algorithms. The results of this case study reveal a potential of about one order of magnitude in energy savings. Furthermore a significant decrease in design time was achieved due to the LISA methodology.