一种用于加速FPGA设计空间探索的电路特性驱动半监督建模方法

摘要

A circuit characteristics-driven semi-supervised modelling approach is proposed for FPGA architecture design space exploration. By including circuit characteristics as input, the proposed approach can estimate the performance of specific circuit on certain architecture accurately. Experimental results illustrate that the approach estimates the area with Mean Relative Error (MRE) up to 6.25%, and delay up to 4.23%, which is comparable to the Semi-supervised Model Tree (SMT) approach. Meanwhile, the proposed approach speedups the modelling process. Compared to the SMT approach, the proposed approach reduces the time cost from 500 h to 250 h when exploring a design space with millions of architectures inside on Intel Xeon E7-4807 platform.%该文提出一种电路特性驱动的半监督建模方法来探索FPGA架构设计空间。通过加入电路特性作为输入来构建一个通用的FPGA性能模型，该方法能够精确预测指定电路在特定FPGA架构上实现的性能。实验结果显示该方法在预测电路在FPGA上实现的面积时，平均相对误差达到6.25%；预测延时时，平均相对误差可达4.23%，具有与半监督模型树(Semi-supervised Model Tree, SMT)方法可比的预测精度。同时，该文方法加速了FPGA性能建模过程，与SMT方法比较，在6核Intel服务器平台Intel Xeon E7-4807上，探索具有百万架构的FPGA设计空间时，该文方法可将时间成本由500 h降低为250 h。