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首页> 外文期刊>Journal of signal processing systems for signal, image, and video technology >Framework for Digital Filter Design Optimization (DiFiDOT) using MCM Based Register Minimization Retiming for Noise Removal ECG Filters
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Framework for Digital Filter Design Optimization (DiFiDOT) using MCM Based Register Minimization Retiming for Noise Removal ECG Filters

机译:使用基于MCM的寄存器最小化重定时实现噪声消除ECG滤波器的数字滤波器设计优化(DiFiDOT)框架

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In all the DSP(Digital Signal Processing) blocks such as digital filters, the filter coefficients are known before hand. Hence, full flexibility of the multiplier is not necessary. Multiplierless Multiple Constant Multiplication(MCM) technique can be used along with retiming for better digital filter optimization.This method is more efficient when compared to shift and add multiplications as intermediate results in MCM technique can be shared which reduces the area of multiplierless implementation of digital filters. The multiplierless filter circuit is further retimed to reduce the overall clock period which increases the clock frequency. Critical path and shortest path computations consume most of the time in retiming computation. The retiming minimizes the overall clock period by reducing the filter critical path. In the general purpose processor where actual retiming vectors are computed for digital filters, the speed with which the retiming transformation is performed suffers as the entire transformation code will be written in the form of a soft core. Hence, FPGA based path solver architecture are proposed in this paper can reduces the burden on general purpose processors while retiming. This work contributes to reduced processing time for retiming using FPGA based path solvers. Due to complexity and transistor size reduction, designing of VLSI architectures for DSP blocks has become very challenging. Automated Tools are required most often to introduce the products to market in a timely manner and to make the VLSI designs more stable, reliable and tractable. A framework called DiFiDOT(Digital Filter Design Optimization Tool) is developed in this work for synthesizing the optimized filter architectures. Finally, an application for Electrocardiography(ECG) is designed using MCM based retimed digital filters to remove the power supply interference, baseline drift and the broadband noise from the ECG signal.
机译:在诸如数字滤波器之类的所有DSP(数字信号处理)模块中,滤波器系数是事先已知的。因此,不需要乘法器的完全灵活性。无乘法器多常数乘法(MCM)技术可与重定时配合使用,以实现更好的数字滤波器优化。与移位和加乘法相比,该方法效率更高,因为可以共享MCM技术的中间结果,从而减少了数字无乘法实现的面积过滤器。无乘法器滤波器电路进一步重新计时,以减少总时钟周期,从而增加时钟频率。在重定时计算中,关键路径和最短路径计算会消耗大部分时间。通过减少滤波器的关键路径,重定时使总时钟周期最小化。在为数字滤波器计算实际重定时矢量的通用处理器中,重定时转换的执行速度会受到影响,因为整个转换代码将以软核的形式编写。因此,本文提出了一种基于FPGA的路径求解器架构,可以减轻通用处理器在重定时时的负担。这项工作有助于减少使用基于FPGA的路径求解器进行重定时的处理时间。由于复杂性和晶体管尺寸的减小,用于DSP模块的VLSI架构的设计变得非常具有挑战性。最需要自动化工具来及时将产品推向市场,并使VLSI设计更加稳定,可靠和易于控制。在这项工作中,开发了一个名为DiFiDOT(数字滤波器设计优化工具)的框架,用于合成优化的滤波器架构。最后,使用基于MCM的重定时数字滤波器设计了一种心电图(ECG)应用程序,以消除ECG信号中的电源干扰,基线漂移和宽带噪声。

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