Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits

摘要

Thermal stress issues in a three-dimensional (3D) stacked wafer system were examined using finite-element analysis of the stacked wafers. This paper elucidates the effects of the bonding dimensions on mechanical failure and the keep-away zone, where devices cannot be located because of the stress in the Si. The key factors in decreasing the thermal strain were the bonding diameter and thickness. When the bonding diameter decreased from 40 μm to 12 μm, the equivalent strain decreased by 83%. It is noteworthy that the keep-away zone also decreased from 17 μm to zero when the bonding diameter decreased from 40 μm to 12 μm. When the bonding thickness doubled, the equivalent strain decreased by 44%. The effects of the dimensions and arrangement of through-silicon vias (TSV) were also analyzed. Small TSV diameter and pitch are important to decrease the equivalent strain, especially when the amount of Cu per unit volume is fixed. When the TSV diameter and pitch decreased fourfold, the equivalent strain decreased by 70%. The effects of TSV height and the number of die stacks were not significant, because the underfill acted as a buffer against thermal strain.