Signal integrity and propagation delay analysis using FDTD technique for VLSI interconnects

摘要

In UDSM technology, on-chip interconnect wires form a complex geometry and introduces wire and coupling parasitics. The coupling parasitics (M, C_C) introduce crosstalk noise which may lead to critical delays/logic malfunctions. This paper analyzes the dependency of crosstalk noise and delay on coupling parasitics for simultaneously switching inputs using FDTD technique. The FDTD method is used because it is a strong mathematical platform for the analysis of time domain behavior of coupled lines. For implementation of FDTD algorithm, discretizations are carried out in time and space both. To ensure stability in FDTD solution, the discrete voltage points are interlaced by current points in both space and time. To validate the proposed method, FDTD computations are carried out and results are compared with those of conventional SPICE results. A good agreement of FDTD results has been observed with respect to SPICE results. An average error of less than 2 % is observed for the proposed FDTD algorithm with respect to SPICE.