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首页> 外文期刊>Journal of circuits, systems and computers >YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs
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YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs

机译:YaNoC:另一个片上网络仿真加速引擎,支持使用FPGA的拥塞感知自适应路由

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摘要

Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the customtopologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the 6 x 6 mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the 6 x 6 mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively.
机译:许多核心系统采用片上网络(NoC)作为基础通信体系结构。为了针对所考虑的应用实现优化设计,需要一种快速灵活的NoC仿真器。本文提出了一种基于FPGA的NoC仿真加速框架,该框架支持考虑了完整的微体系结构参数的标准和自定义NoC拓扑的设计空间探索。该框架能够设计自定义路由算法,支持各种流量模式,例如统一随机,转置,比特补码和随机置换。对于常规NoC,支持标准最小路由算法。为了设计定制拓扑,已经实现了基于表的路由。已经使用基于表的新颖最短路径路由算法评估了称为对角网格的自定义拓扑。已经提出了拥塞感知自适应路由,以沿着最小拥塞路径路由分组。与常规XY路由相比,拥塞感知的自适应路由算法的FPGA区域开销可忽略不计。与XY路由算法相比,采用拥塞感知的自适应路由,网络等待时间减少了55%。微结构参数(例如缓冲区深度,流量模式和碎片宽度)已更改,以观察对NoC行为的影响。对于6 x 6网格拓扑,分别考虑4的缓冲区深度和16位和32位的帧宽度,LUT和FF的使用率将从32.23%增加到34.45%,从12.62%增加到15%。对于缓冲区深度和碎片宽度的其他配置,也观察到了类似的行为。环形拓扑比网状拓扑消耗的资源多24%。与6 x 6网格和环形拓扑相比,具有56个节点的胖树拓扑消耗的FPGA资源多27%和2.2%。缓冲深度为8和16片的56节点胖树拓扑分别以40%和45%的注入速率饱和。

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