On the extraction of interface trap density in the Pt/La2O_3/Ge gate stack and the determination of the charge neutrality level in Ge

摘要

The study of trap densities at the oxide-semiconductor interface of the new generation of field-effect transistors is essential for the optimization of their electrical performance. The conventional conductance method, which was efficiently applied to Si, turns out to be less appropriate on alternative substrates, such as the lower band gap germanium (Ge), because of the strong influence of minority carrier processes. Recent investigations show that these restrictions might be severe and lead to incorrect conclusions. We identify here the appearance of such processes, compare the conventional conductance method with the full conductance method of Martens et al, IEEE Electron Device Lett. 27, 405 (2006), and propose an extension of the latter. By applying a reverse bias to source and drain with respect to the substrate, it becomes possible to separate, on the same device, the contribution of electron and hole trap distributions. Our approach allows us to determine the position of the charge neutrality level at the surface of the semiconductor, which is found to be at 0.14 eV above the valence band.