Electric Properties and Interface Charge Trap Density of Ferroelectric Gate Thin Film Transistor Using (Bi,La)_4Ti_3O_(12)/Pb(Zr,Ti)O_3 Stacked Gate Insulator

摘要

We successfully fabricated ferroelectric gate thin film transistors (FGTs) using solution-processed (Bi,La)_4Ti_3O_(12)/Pb(Zr,Ti)O_3 (PZT) stacked films and an indium-tin oxide (ITO) film as ferroelectric gate insulators and an oxide channel, respectively. The typical n-type channel transistors were obtained with the counterclockwise hysteresis loop due to the ferroelectric property of the BLT/PZT stacked gate insulators. These FGTs exhibited good device performance characteristics, such as a high ON/OFF ratio of 10~6, a large memory window of 1.7-3.1 V, and a large ON current of 0.5-2.5 mA. In order to investigate interface charge trapping for these devices, we applied the conductance method to MFS capacitors, i.e., Pt/ITO/BLT/PZT/Pt capacitors. As a result, the interface charge trap density (D_(it)) between the ITO and BLT/PZT stacked films was estimated to be in the range of 10~(-11)-10~(-12) eV~(-1) cm~(-2). The small D_(it) value suggested that good interfaces were achieved.