The Performance of Magnetic Tunnel Junction Integrated on the Back-End Metal Line of Complimentary Metal-Oxide-Semiconductor Circuits

摘要

In this paper, we have described the complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integrated process technology; MTJs were fabricated on via metal with surface roughness of 0.3nm with 0.14μm CMOS process and 60 × 180nm~2 MTJ process. It is shown that by this process technology, the fabricated MTJ on CMOS logic circuit plane achieves a large change in a resistance of 3.63 kΩ (anti-parallel) with the TMR ratio of 138% at room temperature, which is large enough for a sensing scheme of standard CMOS logic. Furthermore, we have successfully demonstrated the DC and AC operation of this MTJ with write transistors. As the results, our MTJ achieves high enough write/read performance with transistors for realizing MTJ-based logic circuits.