Low-cost and scalable embedded nonvolatile memory using quasi-planar bulk transistor with standard CMOS gate stacks

摘要

We propose a low-cost and highly scalable embedded nonvolatile memory using a quasi-planar bulk transistor fabricated with a standard CMOS process. Program and erase operation was achieved by hot-electron injection into the gate dielectric and drain-assisted hot-hole injection and/or electron ejection, respectively. Thanks to the electric field concentration at the channel corners in quasi-planar bulk transistor, not only the program efficiency, but also the erase efficiency was enhanced with the decrease in channel width. Scaling of gate length also improved the program and erase characteristics. As a result, a threshold voltage window of more than 0.3 V was repeatedly attained. Moreover, 300 program and erase cycles and 10-year data retention were experimentally demonstrated. Thus, quasi-planar bulk Tr. memory was found to be highly suitable for nonvolatile memory embedded with low-power scaled CMOS.