A Design Method for Low Power Arithmetic Circuits and Hiroto Yasuura

摘要

Arithmetic circuits are important components of micro processors and image processing LSIs. Performance of digital signal processors and motion video processors strongly depends On the performance of multipliers. In the design of arithmetic circuits, 1bit full adders and counters are used as basic cells. In this paper we propose a design method for low power arithmetic circuits in which 1) basic cells are selected from a set of circuits with different structures and 2) connections to the terminals of the basic cells are optimized. Experimental results demonstrates 32.1/100 power reduction of a parallel multiplier designed by the proposed technique.