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Arithmetic processing device, arithmetic processing device design method, and logic circuit design method

机译:算术处理装置,算术处理装置设计方法以及逻辑电路设计方法

摘要

In order to realize an arithmetic device that reduces the number of elements of the arithmetic circuit and the delay time by a purely logical approach, the arithmetic operation method by encoding is specifically and efficiently designed to provide an encoded arithmetic device. If necessary, the arithmetic unit is expanded and treated as a logical function of the radix r. When r = 2, a generating function that is a new expression of the mapping is used, and under the encoding condition and the logical expression simplification condition The new arithmetic system is designed logically or the topology of the input / output relationship between the arithmetic unit of the original arithmetic system and the new arithmetic system is matched to design a new arithmetic system of the encoding arithmetic method. An arithmetic processing device that satisfies the encoding conditions and the logical expression simplification achieves high speed and low power consumption.
机译:为了通过纯逻辑方法实现减少算术电路的元件数和延迟时间的算术装置,特别有效地设计了通过编码的算术运算方法以提供编码的算术装置。如有必要,可扩展算术单元并将其视为基数r的逻辑函数。当r = 2时,将使用作为映射的新表达式的生成函数,并在编码条件和逻辑表达式简化条件下使用新的算术系统或在逻辑上设计算术单元之间的输入/输出关系的拓扑匹配原始算术系统和新算术系统,以设计编码算术方法的新算术系统。满足编码条件和逻辑表达式简化的算术处理装置实现了高速和低功耗。

著录项

  • 公开/公告号JPWO2004068364A1

    专利类型

  • 公开/公告日2006-05-25

    原文格式PDF

  • 申请/专利权人 マセマテック株式会社;

    申请/专利号JP20050504692

  • 发明设计人 渡 雅男;

    申请日2004-01-26

  • 分类号G06F17/10;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 21:49:13

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