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Arithmetic processing device, arithmetic processing device design method, and logic circuit design method

机译:算术处理装置,算术处理装置设计方法以及逻辑电路设计方法

摘要

An operation device having the element number and delay time of the operation circuitry reduced is realized by a purely logical approach. An operation method based on encoding is concretely and efficiently logic-designed to provide an encoding operation device. operators of an operation system are extended if required to treat as logic functions with the base number r. When r=2, using a generating function as a new representation of a mapping, a new operation system is logic-designed under encoding conditions and logic expression simplifying conditions, or the new operation system is logic-designed by matching the topologies of input/output relation of the operators of the original operation system and the new operation system. The operation device satisfying the encoding conditions and logic expression simplifying conditions achieves speeding up and low power consumption. IMAGE
机译:通过纯粹的逻辑方法实现了减少了运算电路的元件数量和延迟时间的运算装置。具体和有效地逻辑设计基于编码的运算方法,以提供一种编码运算装置。如果需要将操作系统的运算符扩展为具有基数r的逻辑功能,则可以对其进行扩展。当r = 2时,使用生成函数作为映射的新表示形式,可以在编码条件和简化逻辑表达式的条件下对新操作系统进行逻辑设计,或者通过匹配输入/输出拓扑来逻辑设计新操作系统。原始操作系统和新操作系统的操作员的输出关系。满足编码条件和逻辑表达式简化条件的操作装置实现了加速和低功耗。 <图像>

著录项

  • 公开/公告号JP4445921B2

    专利类型

  • 公开/公告日2010-04-07

    原文格式PDF

  • 申请/专利权人 マセマテック株式会社;

    申请/专利号JP20050504692

  • 发明设计人 渡 雅男;

    申请日2004-01-26

  • 分类号G06F17/10;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 18:57:21

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