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A Low-Power Multichannel Time-to-Digital Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR Sensors

机译:使用具有50-PE分辨率的全数字嵌套延迟锁定环路和LIDAR传感器的高吞吐量的低功耗多通道时间 - 数字转换器

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This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through a coarse counter, middle, and fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle and fine all-digital delay-locked loops (ADDLLs) is provided to ensure the stability of the generated time slots. Charge pump, loop filter, and voltage-controlled delay line inside the conventional analog delay-locked loops (DLLs) are replaced by an accumulator (ACC) and digitally controlled delay line (DCDL). This makes the design particularly compact, low power, and suitable for multichannel applications. The presented architecture can generate information for amplitude variation (walk error) compensation. This information is generated by measuring the pulsewidth and position of three successive STOP pulses inside each channel within a single-shot measurement. A low-jitter injection-locked frequency multiplier (ILFM) generates a 625-MHz internal clock signal out of 25-MHz external reference oscillator, which shrinks the number of delay elements to cover one period of the reference clock and improves the precision of the TDC. Operation at higher frequency provides high throughput and short conversion time (less than 3 ns). The three-level TDC offers 13.1-mu s maximum input range and 50-ps resolution. The measured DNL and INL of the TDC circuit are 0.47 and 0.71 LSB, respectively. The TDC circuit is implemented in a 180-nm standard CMOS process with a die size of 1.5 mm x 1.5 mm. The total power consumption of the multichannel TDC is 87.6 mW.
机译:本文介绍了低功耗,全数字多通道时间转换器(TDC),用于光检测和测距(LIDAR)传感器。所提出的TDC架构通过粗略计数器,中间和基于精细延迟线的内插技术(Nutt方法)测量时间间隔。通过中间和精细的全数字延迟锁定环(ADDLLS)自动校准以确保所生成的时隙的稳定性。电荷泵,环路滤波器和常规模拟锁定环内的电压控制延迟线(DLL)由蓄电池(ACC)和数字控制的延迟线(DCDL)取代。这使得设计特别紧凑,低功耗,适用于多通道应用。呈现的架构可以生成幅度变化(步行错误)补偿的信息。通过测量单次测量内的每个通道内的三个连续停止脉冲的脉冲宽度和位置来产生该信息。低抖动注射锁定频率倍增器(ILFM)产生25 MHz外部参考振荡器的625 MHz内部时钟信号,从而缩小延迟元件的数量,以覆盖参考时钟的一个时段并提高TDC。较高频率的操作提供高吞吐量和短转换时间(小于3 ns)。三级TDC提供13.1亩的最大输入范围和50-PS分辨率。 TDC电路的测量DNL和INL分别为0.47和0.71LSB。 TDC电路以180nm标准CMOS工艺实现,管芯尺寸为1.5mm×1.5mm。多通道TDC的总功耗为87.6兆瓦。

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