A Hardware/Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Filer

摘要

In digital signal processing, bit width of inter- mediate variables should be longer than that of input and output variables in order to execute intermediate operations with high precision. Then a processor core for digital signal processing is required to have two types of register files. One of which is used by input and output variables and the other one is used by interme- diate variables. This paper proposes a hardware/software cosyn- thesis system for digital signal processor cores with two types of register files.