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A hardware efficient control of memory addressing for high-performance FFT processors

机译:高性能FFT处理器的存储器寻址的硬件有效控制

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摘要

The conventional memory organization of fast Fourier transform (FFT) processors is based on Cohen's (1976) scheme. Compared with this scheme, our scheme reduces the hardware complexity of address generation by about 50% while improving the memory access speed. Much power consumption in memory is saved since only half of the memory is activated during memory access, and the number of coefficient access is reduced to a minimum by using a new ordering of FFT butterflies. Therefore, the new scheme is a superior solution to constructing high-performance FFT processors.
机译:快速傅立叶变换(FFT)处理器的常规内存组织基于Cohen(1976)方案。与该方案相比,我们的方案将地址生成的硬件复杂度降低了约50%,同时提高了内存访问速度。由于在存储器访问期间仅激活了一半的存储器,因此节省了存储器中的大量功耗,并且通过使用新的FFT蝴蝶排序将系数访问的次数减少到最少。因此,新方案是构建高性能FFT处理器的绝佳解决方案。

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