应用于UWB系统的低硬件开销128点FFT处理器设计

摘要

快速傅里叶变换(Fast Fourier transform, FFT) 处理器是数字信号处理领域的核心单元.本文针对超宽带(Ultra wideband, UWB) 系统提出了一种低硬件开销的128点FFT处理器设计方案.此方案在算法上采用了混合基-24-23算法, 硬件实现上采用了单路延迟负反馈(Single delay feedback, SDF) 流水线架构, 在处理复数乘法运算上, 提出一种新型串接正则有符号数(Canonical signed digit, CSD) 常数乘法器替代常用布斯乘法器对旋转因子W1i28的复数乘法运算进行实现, 大幅降低了FFT处理器消耗的硬件资源.本文设计基于QUARTUS PRIME平台进行开发, 并搭配Cyclone 10 LP系列器件, 编译报告显示本文方案对比于其他已存在的方案, 具有最低的硬件开销和功耗.%Fast Fourier transform (FFT) is a key block in the field of digital signal processing (DSP). A low hardware-cost 128-point FFT for UWB system is presented in this paper. Mixed radix-24-23 algorithm is adopted, and single-path delay feedback (SDF) architecture is used for hardware implementation. A novel cascade canonical signed digit (CSD) multiplier is proposed for the complex multiplication of Wi128 instead of the common booth multiplier, which can significantly reduce the hardwarecost. Based on QUARTUS PRIME tool with Cyclone 10 LP, the proposed scheme is developed, and the compilation report shows that the proposed scheme has the least hardware-cost and power consumption compared with the existing schemes.