Design of Power-efficient Memory-based FFT Processor with New Memory Addressing Scheme

摘要

This paper presents a new memory-addressing scheme for the realization of power-efficient memory-based FFT processors. The scheme is based on the minimization of the coefficient access and reduction of switching activity by modifying the butterfly sequence. It also results in reducing hardware scale and shortening the critical path delay. Therefore, the power consumption in complex multiplier and memory is reduced