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首页> 外文期刊>Microwave Theory and Techniques, IEEE Transactions on >A Millimeter-Wave CMOS Triple-Band Phase-Locked Loop With A Multimode LC-Based ILFD
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A Millimeter-Wave CMOS Triple-Band Phase-Locked Loop With A Multimode LC-Based ILFD

机译:具有基于LC的多模LCFD的毫米波CMOS三频带锁相环

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A millimeter-wave multiband phase-locked loop (PLL) is presented for the first time, which covers 40-, 60-, and 80-GHz bands. Three voltage-controlled oscillators corresponding to different frequencies are input to a multiband injection-locked frequency divider and switched on one at a time by a multiplexer as a band selector. The feedback loop embraces the following components: a chain of dividers with a fixed division-modulus of 256, a phase-frequency detector, a charge-pump, and a second-order loop filter. The PLL is clocked by a reference frequency of 78 MHz and its output power is higher than $-{hbox{9.5 dBm}}$. The phase noise is $-{hbox{103 dBc/Hz}}$ at an offset frequency of 10 MHz. With a supply voltage of 1.5 V, the entire PLL consumes 114 mW. The chip is implemented in a 90-nm CMOS technology and measures ${hbox {1.12 mm}}^{2}$.
机译:首次展示了毫米波多频带锁相环(PLL),它涵盖了40、60和80 GHz频段。对应于不同频率的三个压控振荡器被输入到多频带注入锁定分频器,并通过作为频带选择器的多路复用器一次接通一个。反馈环路包含以下组件:固定除法模数为256的分频器链,相频检测器,电荷泵和二阶环路滤波器。 PLL由78 MHz的参考频率作为时钟源,其输出功率高于$-{hbox {9.5 dBm}} $。在10 MHz的偏移频率下,相位噪声为$-{hbox {103 dBc / Hz}} $。在1.5 V的电源电压下,整个PLL消耗114 mW。该芯片采用90纳米CMOS技术实现,尺寸为{{hbox {1.12 mm}} ^ {2} $。

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