The Improvement of High-$k$/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure

摘要

The impact of the Si cap/SiGe layer on the Hf-based high-$k$ /metal gate SiGe channel pMOSFET performance and reliability has been investigated. We proposed an optimized strain SiGe channel with a Si cap layer to overcome the Ge diffusion and confine the channel carriers in the strained SiGe layer without the formation of a significant parasitic channel at the interface. With this optimized Si/SiGe stack channel, a high-performance Hf-based high-$k$/metal gate SiGe pMOSFET can be obtained with an appropriate $V_{rm TH}$ ( $sim$0.3 V), low $C$ –$V$ hysteresis ( $<$ 5 mV), and better $I_{rm ON} - I_{rm OFF}$ , $V_{rm TH}$ rolloff, and $V_{rm TH}$ stability. By the way, the related interface trap density in the high-$k$ gate stack layer can also be reduced, thus improving the device's NBTI and HCI stressing-induced reliability.