A Layout-Level Approach to Evaluate and Mitigate the Sensitive Areas of Multiple SETs in Combinational Circuits

摘要

Multiple single-event transients (MSETs) are evaluated from the perspective of sensitive area. First, a simple model is proposed to analyze the sensitive area of simple logic cells. Based on this simple model, the vulnerabilities of MSETs sensitive areas are then calculated. At last, a layout-level approach is designed to reduce the vulnerabilities of the MSETs sensitive areas. Our simulation results present that this layout-level approach could efficiently reduce the occurrence chance of MSETs.