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Sequential circuit fault simulation using logic emulation

机译:使用逻辑仿真的顺序电路故障仿真

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A fast fault simulation approach based on ordinary logic emulation is proposed. The circuit configured into our system that emulates the faulty circuit's behaviour is synthesized from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection scan chain or by selecting the output of a parallel fault injection selector, with which we get rid of the time-consuming bit-stream regeneration process. Experimental results for ISCAS-89 benchmark circuits show that our serial fault emulator is about 20 times faster than HOPE. The speedup grows with the circuit size by our analysis. Two hybrid fault emulation approaches are also proposed. The first reduces the number of faults actually emulated by screening off faults not activated or with short propagation distances before emulation, and by collapsing nonstem faults into their equivalent stem faults. The second reduces the hardware requirement of the fault emulator by incorporating an ordinary fault simulator.
机译:提出了一种基于普通逻辑仿真的快速故障仿真方法。我们系统中配置的模拟故障电路行为的电路以一种新颖的方式从好的电路和给定的故障列表中合成出来。通过转移故障注入扫描链的内容或选择并行故障注入选择器的输出,可以使故障注入变得容易,从而消除了费时的比特流再生过程。 ISCAS-89基准电路的实验结果表明,我们的串行故障仿真器比HOPE快20倍。根据我们的分析,加速随着电路尺寸的增加而增长。还提出了两种混合故障仿真方法。第一种方法是通过在仿真之前筛选掉未激活的故障或传播距离短的故障,并将非茎干故障折叠成等效的茎干故障,从而减少实际仿真的故障数量。第二个通过合并普通的故障模拟器来降低故障模拟器的硬件需求。

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