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首页> 外文期刊>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems >Single-fault fault-collapsing analysis in sequential logic circuits
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Single-fault fault-collapsing analysis in sequential logic circuits

机译:顺序逻辑电路中的单故障倒塌分析

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摘要

A study is made of single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are analyzed and found to cause the dominance relationship which is valid in combinational circuits but no longer valid in sequential circuits. A fault-collapsing procedure is proposed to collapse faults in sequential circuits. It first collapses faults in the non-SAD (self-hiding and delayed-reconvergence) gates of the combinational part of the sequential circuit and then further collapses faults by identifying the prime fan-out branches. Finally, it collapses faults in feedback lines. The collapsed faults constitute a sufficient representative set of prime faults.
机译:对顺序逻辑电路中发生的单故障故障进行了研究。分析了两个主要现象,即自隐藏(SH)和延迟再收敛(DR),它们是由于时序电路中存在反馈路径和存储元件而引起的,并且导致了在组合电路中有效但不再存在的优势关系在顺序电路中有效。提出了一种故障折叠程序,以消除时序电路中的故障。它首先使时序电路组合部分的非SAD(自隐藏和延迟再收敛)门中的故障崩溃,然后通过识别主要扇出分支进一步使故障崩溃。最后,它使反馈线路中的故障崩溃。坍塌的断层构成了一组具有代表性的原始断层。

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