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Pad Assignment for Die-Stacking System-in-Package Design

机译:芯片堆叠系统级封装设计的焊盘分配

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Wire bonding is currently the most popular method for connecting signals between dies in system-in-package (SiP) design. Pad assignment, which assigns inter-die signals to die pads so as to facilitate wire bonding, is an important physical design problem for SiP design because the quality of a pad assignment solution affects both the cost and the performance of an SiP design. In this paper, we study a pad assignment problem, which prohibits the generation of illegal crossings and aims to minimize the total signal wirelength, for die-stacking SiP design. We first consider the two-die cases and die-stacks with a bridging die, and present a minimum-cost flow-based approach to optimally solve them in polynomial time. We then describe an approach, which uses a modified left-edge algorithm and an integer linear programming technique, for pyramid die-stacks with no bridging die. Finally, we discuss extensions of the two approaches to handle additional design constraints. Encouraging experimental results are shown to support our approaches.
机译:引线键合是当前最流行的在系统级封装(SiP)设计中在管芯之间连接信号的方法。焊盘分配可将管芯间的信号分配给芯片焊盘,以促进引线键合,这是SiP设计的重要物理设计问题,因为焊盘分配解决方案的质量会影响SiP设计的成本和性能。在本文中,我们研究了用于SiP叠层设计的焊盘分配问题,该问题可防止非法交叉的产生,并旨在最大程度地减小总信号线长。我们首先考虑带有桥头模具的两个模具的情况和模具堆,然后提出一种基于最小成本的基于流程的方法,以在多项式时间内对其进行最佳求解。然后,我们描述一种方法,该方法使用改进的左边缘算法和整数线性编程技术,用于没有桥接芯片的金字塔芯片堆栈。最后,我们讨论了两种方法的扩展,以处理其他设计约束。令人鼓舞的实验结果表明可以支持我们的方法。

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