This paper presents a new family of logic gates for low energy computing using pulsed power CMOS logic. The logic gates use the principles of adiabatic-switching and results show that in typical cases 90% of the energy can be recovered with operating frequency around 1 MHz. Constant capacitance condition is enforced in our designs so that signals' energy can be efficiently recycled in the chip. We also present a detailed analysis and modeling of energy dissipation in adiabatic circuits. The models were experimentally validated using the circuit simulator SPICE. A simplified version of adiabatic logic with simplicity comparable to static CMOS circuits is also presented. For a 2/spl times/2 multiplier using this type of logic, 60% of energy can be saved over static CMOS case at 20 MHz and there is 35% less energy consumption at 100 MHz.
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机译：本文介绍了使用脉冲功率CMOS逻辑进行低能耗计算的新逻辑门系列。逻辑门使用绝热开关原理，结果表明，在典型情况下，工作频率约为1 MHz时，可以回收90％的能量。在我们的设计中强制采用恒定电容条件，以便可以在芯片中有效地回收信号能量。我们还提出了绝热电路中能量耗散的详细分析和建模。使用电路仿真器SPICE对模型进行了实验验证。还提出了绝热逻辑的简化版本，其简化程度可与静态CMOS电路相媲美。对于使用这种逻辑的2 / spl times / 2乘法器，在20 MHz的静态CMOS情况下可以节省60％的能量，而在100 MHz的情况下可以节省35％的能耗。
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