A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method

摘要

This paper presents a time-to-digital converter (TDC) using a fractional difference conversion scheme. Two delay-locked loops (DLLs) provide negative feedbacks to stabilize the delays against process and ambient variations. In addition, by adopting the principles of cyclic Vernier delay line, the resolution is improved while dynamic range is significantly increased. The proposed TDC architecture is competitive in terms of resolution and power compared to the other DLL/PLL stabilized TDCs. The TDC designed and fabricated in 0.18 $mu hbox{m}$ CMOS process achieves a 14.6 ps resolution as well as a 50 ns dynamic range, while consuming 6.4 mW power.