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Fast Sensing-Time and Hardware-Efficient Eigenvalue-Based Blind Spectrum Sensors for Cognitive Radio Network

机译:基于快速的传感时间和硬件高效的基于硬件的认知无线网络盲谱传感器

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This paper presents implementation friendly VLSI-algorithms for maximum-eigenvalue-detection (MED), energy with minimum-eigenvalue (EME), and mean-to-square extreme-eigenvalue (MSEE) based blind spectrum sensing algorithms. We propose to use efficient iterative power-method for computing maximum and minimum eigenvalues for these algorithms that complemented our hardware design. New VLSI architectures based on suggested spectrum sensing algorithms have been presented in this work. We present two types of sensor architectures: (1) memory-less & low-latency (2) memory-based & resource-shared spectrum-sensor architectures. Former type targets to achieve lower sensing time with adequate hardware efficiency and the later ones are highly resource shared to consume lesser hardware with moderate sensing time. Performance analyses of suggested MED, MSEE and EME spectrum sensing algorithms in AWGN environment showed that the detection probability of 0.75 could be achieved at the SNRs of -12 dB, -10 dB and -7 dB respectively. On synthesizing and post-layout simulating our sensor architectures in 90 nm-CMOS process with the supply of 1.2 V, they could operate at the maximum clock frequency up to 408 MHz delivering sensing time in the range of 23-44 mu s. The proposed spectrum sensors have achieved 5.5x and 19x better sensing time and hardware efficiency, respectively, compared to the state-of-the-art implementations. Eventually, the memory-based spectrum sensors are FPGA prototyped and tested, at 100 MHz clock frequency, in DVB-T signal environment with OFDM modulated transmitted signals in 2K size IFFT-mode.
机译:本文介绍了实现友好的VLSI算法,用于最大 - 特征值 - 检测(MED),具有最小特征值(EME)的能量,以及基于盲光谱传感算法的平均盲目的极端特征值(MSEE)。我们建议使用高效的迭代电源方法来计算补充我们的硬件设计的这些算法的最大和最小特征值。在这项工作中介绍了基于建议的频谱感测算法的新VLSI架构。我们介绍了两种类型的传感器架构:(1)基于内存和资源共享频谱传感器架构的内存较少和低延迟(2)。以前的类型目标以充分的硬件效率实现较低的传感时间,并且后来的是具有适中的激动时间的高度资源,以消耗更小的硬件。 AWGN环境中建议的MED,MSEE和EME谱检测算法的性能分析表明,0.75的检测概率分别可以在-12dB,-10dB和-7dB的SNR处实现。在合成和后布局模拟90 NM-CMOS过程中的传感器架构,供应1.2 V,它们可以在最大时钟频率下运行,高达408 MHz的传感时间在23-44亩的范围内。与最先进的实施方式相比,所提出的频谱传感器分别实现了5.5倍和19倍的感测时间和硬件效率。最终,基于内存的频谱传感器是FPGA在DVB-T信号环境中以100MHz时钟频率测试的FPGA,在2K尺寸IFFT模式下使用OFDM调制传输信号。

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