A 1-MHz Relaxation Oscillator Core Employing a Self-Compensating Chopped Comparator Pair

摘要

An improved relaxation oscillator core is designed and fabricated in 0.35-mu m CMOS process, occupying the area of 0.032 mm(2) and consuming around 160 mu W while running at 1 MHz. Employing a self-compensating chopped comparator structure, the designed oscillator exhibits a significant improvement in the frequency stability and control linearity, at the same time retaining a fast start-up and having a minimal overhead in the power consumption and area. Measured on 8 test chips, the frequency variation against temperature is +/- 0.26% in the temperature range from -40 to 125 degrees C, and the line sensitivity is +/- 0.08 %/V with the supply voltage changing from 3.0 to 4.5 V. The typical distortion parameters of the control characteristic are HD2 = -61.7 dB and HD3 = -93.2 dB at Delta f(osc) = 500 kHz. The measured jitter and phase noise at 10 kHz carrier offset are 235 ppm and -92 dBc/Hz, respectively, while the Allan deviation floor is 15 ppm.