An 18–23 GHz 57.4-fs RMS Jitter −253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique

摘要

This paper proposes a sub-harmonically injection-locked all-digital PLL (SIL-ADPLL). The SIL-ADPLL includes five main circuit blocks: injection-locked digitally controlled oscillator with single-ended injection technique (SILDCO), injection-locked frequency divider (ILFD), timing-adjusted phase detector (TPD), multiplexed time-to-digital converter (MTDC), and the pulse generator (PG). The single-ended injection technique relaxes the pulse width constraint of the injection pulse and thus reduces the design complexity of PG. The proposed ILFD aided injection timing alignment technique can align the injection timing adaptively at output frequency higher than 20 GHz. The ILFD block is inserted between the SILDCO and the TPD without much penalty of power consumption. The proposed MTDC can quantize the output of TPD with only one TDC core to further save power consumption. The proposed PG can relax the trade-off between the phase noise suppression and the power consumption. Implemented in 65 nm CMOS process with a core area of 0.462 mm(2), the SIL-ADPLL achieves 18- to 23-GHz frequency range, 57.4-fs rms jitter at 20 GHz, 13.7-mW power consumption, and -253.5-dB FoM. The measurement results also show robustness over environment variation.