An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter

摘要

An injection-locked phase-locked loop (ILPLL) which continuously tracks the injection timing to achieve improved jitter performance is presented. When the injection timing is not precisely matched with the edges of the oscillator clock, the performance of ILPLL such as jitter and reference spur degrades significantly. To find an optimum injection timing, a calibration technique is proposed that continuously monitors the error information from the bang-bang phase and frequency detector when the injection of the reference clock is intentionally omitted every other cycle. The timing calibrator enables a robust ILPLL operation over the process, voltage, and temperature variations. The proposed ILPLL fabricated in 28-nm CMOS technology occupies 0.03 mm^{2and consumes 5.65 mW at 5 GHz with 0.9-V supply voltage. The measured jitter integrated from 1 kHz to 40 MHz is 152 fs, and the spur levels at the reference and 2nd subharmonic are −62 dBc and −53 dBc, respectively.}