PLL CIRCUIT, A COMMUNICATION DEVICE, AND A METHOD FOR TESTING LOOPBACK OF THE COMMUNICATION DEVICE, CAPABLE OF ATTENUATING A HIGH FREQUENCY JITTER COMPONENT USING A CLOSED LOOP FREQUENCY CHARACTERISTIC OF THE PLL

摘要

PURPOSE: A PLL circuit, a communication device, and a method for testing loopback of the communication device are provided to transit a modulation degree of an SSC by suppressing a jitter of the SSC.;CONSTITUTION: A phase comparison unit(10) generates a control voltage according to the phase difference between a reference clock signal and a feedback clock signal. A voltage controlled oscillator(14) generates an output clock signal by oscillating in an oscillation frequency according the control voltage. A phase interpolator(15) generates a phase shifted signal by shifting the phase of an output clock signal corresponding to the phase shift quantity selected from a plurality of different phase shift quantities. A frequency divider generates a feedback clock signal by dividing the frequency of the phase shifted signal. A control unit controls the phase interpolator for gradually changing the phase shift quantity.;COPYRIGHT KIPO 2010