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Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique

机译:高速时交错子测距SAR ADC的最优码传输技术设计

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摘要

This paper discusses design methodologies for highspeed SAR ADCs. A comparison of various architectures and the study of benefits and limits identify the best solution for highspeed and medium resolution. It is an interleaving architecture with the channel implemented by a fast coarse SAR quantizer and 2-way time-interleaved (TI) fine SAR ADCs. We propose a floatthen-write code transfer technique for optimizing the transfer sequence and reducing the reference interference. Furthermore, we also study and compare the output impedance of the reference generation as well as the reference interference for the optimized code transfer scheme and the conventional bit-by-bit in both single-channel and TI scenarios. In addition, the mismatches in TI channels and two sub-ADCs are discussed. A 10-bit test vehicle fabricated in 65-nm CMOS confirms experimentally the proposed methods operating with 1.2-V supply at 700 MS/s. The circuit occupies an active area of 0.084 mm(2) and achieves a signalto-noise and distortion ratio at a Nyquist of 53.3 dB, with a power consumption of 9.5 mW. The Walden figure-of-merit is 36 fJ/conversion-step.
机译:本文讨论了高速SAR ADC的设计方法。对各种体系结构的比较以及对收益和限制的研究确定了高速和中分辨率的最佳解决方案。它是一种交错架构,其通道由快速粗略SAR量化器和2路时间交错(TI)精细SAR ADC实现。我们提出了一种浮点写代码传输技术,以优化传输顺序并减少参考干扰。此外,在单通道和TI场景中,我们还研究和比较了参考代的输出阻抗以及优化代码传输方案和常规逐位的参考干扰。此外,还讨论了TI通道和两个子ADC中的失配。用65纳米CMOS制造的10位测试工具在实验上证实了所建议的方法在1.2伏电源下以700 MS / s的速度运行。该电路的有效面积为0.084 mm(2),在奈奎斯特(Nyquist)为53.3 dB时实现了信噪比和失真比,功耗为9.5 mW。 Walden的品质因数为36 fJ /转换步长。

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  • 作者单位

    Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Fac Sci & Technol, Dept Elect & Comp Engn, Macau 999078, Peoples R China;

    Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Fac Sci & Technol, Dept Elect & Comp Engn, Macau 999078, Peoples R China;

    Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Fac Sci & Technol, Dept Elect & Comp Engn, Macau 999078, Peoples R China;

    Univ Pavia, Dept Elect, I-27100 Pavia, Italy;

    Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Fac Sci & Technol, Dept Elect & Comp Engn, Macau 999078, Peoples R China;

    Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Fac Sci & Technol, Dept Elect & Comp Engn, Macau 999078, Peoples R China;

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  • 正文语种 eng
  • 中图分类
  • 关键词

    SAR ADC; time-interleaved scheme; two-step SAR conversion; reference interference;

    机译:SAR ADC;时间交错方案;两步SAR转换;参考干扰;

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