Implementation of a Self-Timed Segmented Bus

摘要

Modern deep-submicron silicon technologies permit increasingly complex SoC designs. The growing diversity of devices results in many possible interfaces. Often, the interconnection complexity of SoC modules limits both the system design process and system performance. Furthermore, these modules often require different data transfer speeds and parallel transmission capability. A conventional bus structure might not be adequate for these demands because, typically, only one attached module can transmit at a time, and a large capacitive load caused by attached system modules and long bus wires can make a bus very slow. Moreover, the increase in both functional complexity and size of modern SoC devices tends to lengthen interconnect wires between system modules. As a result, synchronous system timing based on global clocks will become more difficult, if not impossible. A viable solution to these problems is a segmented-bus architecture based on asynchronous communication. Such a structure provides a flexible platform for asynchronous self-timed SoC design, including globally asynchronous, locally synchronous designs in which each distinct system module has a self-timed interface but is internally synchronized to a local optimized clock. A self-timed interface method significantly improves system composability and scalability, automatically removing the difficult problems related to global clock distribution. Moreover, partitioning the bus into several concurrently operating segments overcomes the performance bottleneck of a conventional bus, letting modules in a particular segment exchange data independently of modules in other segments. Simple bridges composed of tristate buffers isolate adjacent bus segments from each other. Whenever an intersegment transfer occurs, these bridges dynamically link several successive segments to establish a connection between modules in different segments. Researchers proposed the concept of segmenting buses primarily for multicomputer architectures. More recent approaches address on-chip implementation of segmented buses. This article presents an asynchronous segmented-bus architecture targeted for the modular design of high-performance SoC applications. The structure not only enables faster operation than a conventional bus system but also offers lower power consumption per transferred data item. This is possible because segmentation is realized in such a way that the majority of data transfers in the system are intrasegment transactions on relatively short wires with low or moderate capacitive loads.