Design and FPGA Implementation of Self-Timed Wave-Pipelined Filters with Distributed Arithmetic Algorithm

摘要

increased speeds are achieved in the pipelined filters at the cost of an increase in the number of slices by 15-33% and in the number of registers by 350-530%. To compare the power dissipation, both pipelined and wave-pipelined DA filters are tested by operating them at the same frequency. For medium logic depths, the wave-pipelined DA filters dissipate less power than pipelined filters.