This paper explores the implementation of both the Decimating and Interpolating multi-rate fillter structures in the Xilinx XC4000E/XL FPGA architecture.A complete example that demonstrates the computational advantages is presented.The example covers the entire design process from system-level definition through the design and implementation phases.The unique advantages such as very-high performance and in-circuit re-configuration that the Xilinx XC4000E/XL architecture provides is also discussed.The example will contrast the implementation of a single rate narrow-band 27-MHz 119-tap FIR filter with that of a cascaded multi-rate FIR filter implementation.The cascaded multi-rate implementation will utilize a decimating FIR filter structure operating at the reduced sample rate to implement the narrow-band filter.The filtered signal is then passed through an up-sampler interpolating FIR filter to represent the band-limited signal at the original sample rate.The interpolating FIR filter structure also operates at the lower sampling rate.The differences,such as circuit size,cost,and performance between the standard monolithic single-rate 27 MHz 119-tap FIR filter and the cascaded multi-rate FIR filters are discussed.
展开▼
