基于FPGA的高速FIR滤波器并行结构设计

摘要

Based on FPGA, a new finite impulse response (FIR) filter structure is proposed, which increases the capability of processing by N (the number of subfilters) times compared with the serial FIR filter, and decreases the corresponding delay, with low clock rate, the throughout is highly improved by the parallel FIR filter. Under the background of the Wideband Data Chaining, the implement and application of the parallel FIR filter are introduced. An example of the floating point parallel 2-channel FIR filter is given to verify the algorithm on Matlab. Then a fixed point parallel FIR filter is designed on the Xilinx's K7 chips ,which has optimum canonical signed digits coefficients. Compiling and deployment results show that the pareallel FIR filters run at the sampling rate up to 1GHz on the Xilinx's Vivado.%提出了一种基于FPGA平台的并行FIR滤波器结构,能大幅提升滤波器的计算能力.与传统的串行滤波器结构相比,并行结构的运算速度可以提高N倍,N为并行路数,同时运算延迟也会相应减小,在处理时钟速率有限的情况下,通过使用并行结构的FIR滤波器,可大幅提高运算吞吐量.以宽带数据链为应用背景介绍了并行FIR滤波器的使用与实现,以两路并行结构设计为例,通过Matlab对FIR滤波器运算进行了浮点级的仿真验证,然后用经典符号数表示以及优化定点滤波器系数,最后在Xilinx的K7系列芯片实现了定点并行滤波器.通过Xilinx提供的编译软件Vivado编译以及下载测试结果表明,该滤波器仅占用少量的资源,其等效吞吐量可达到1GHz.