A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

Gabriel Torrens; Bartomeu Alorda; Cristian Carmona; Daniel MalagÓn-PeriÁnez; Jaume Segura; Sebastia Bota

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A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

机译：具有最小尺寸晶体管的65nm可靠6T CMOS SRAM单元

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As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on area, power, perfor

机译：由于使用单元比和上拉比为1时可获得最小面积的SRAM位单元，因此我们分析了将单元比从传统值（介于1.5-2.5到1之间）减小的可能性。功率，性能

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来源
《Emerging Topics in Computing, IEEE Transactions on》 |2019年第3期|447-455|共9页
作者
Gabriel Torrens; Bartomeu Alorda; Cristian Carmona; Daniel MalagÓn-PeriÁnez; Jaume Segura; Sebastia Bota;
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作者单位

Electronics Systems Group Physics University of the Balearic Islands Palma de Mallorca Spain;

Electronics Systems Group Physics University of the Baleari;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Transistors; Circuit stability; Stability analysis; Inverters; SRAM cells; Layout;

机译：晶体管;电路稳定性;稳定性分析;逆变器SRAM单元布局;

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1. Carbon Nanotube-Based CMOS SRAM: 1 kbit 6T SRAM Arrays and 10T SRAM Cells [J] . Kanhaiya Pritpal S., Lau Christian, Hills Gage, IEEE Transactions on Electron Devices . 2019,第12期

机译：基于碳纳米管的CMOS SRAM：1 kbit 6T SRAM阵列和10T SRAM单元
2. Transistor Width Effect on the Power Supply Voltage Dependence of α-SER in CMOS 6T SRAM [J] . Torrens G., Alheyasat A., Alorda B., IEEE Transactions on Nuclear Science . 2020,第5期

机译：晶体管宽度对CMOS 6T SRAM中α-Ser的电源电压依赖性的影响
3. A 256-Kb Dual-${V}_{rm CC}$ SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor [J] . Khellah M., Somasekhar D., Ye Y., IEEE Journal of Solid-State Circuits . 2007,第期

机译：采用有源钳位睡眠晶体管的65nm CMOS工艺中的256-Kb Dual-$ {V} _ {rm CC} $ SRAM构造模块
4. −197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOS [C] . A. Jha, A. Ahmadi, S. Kshattry, Symposium on VLSI Circuits . 2016

机译：−197dBc / Hz FOM 4.3-GHz VCO在65-nm CMOS中使用最小尺寸的nmos交叉耦合晶体管对的可寻址阵列
5. Performance Analysis of 7nm FinFET Based 6t SRAM Cell – Transient and DC Analysis [D] . Khan, Sheebasamreen. 2021

机译：基于7NM FinFET的6T SRAM细胞瞬态和DC分析性能分析
6. A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process [O] . Meng-Yin Hsu, Chu-Feng Liao, Yi-Hong Shih, 2017

机译：采用纯CMOS逻辑工艺的具有自抑制电阻切换负载的RRAM集成4T SRAM
7. A Comparative Analysis of 6T and 10T SRAM Cells for Sub-threshold Operation in 65 nm CMOS Technology [O] . Hosseini-Salekdeh Seyed-Rambod 2016

机译：用于65 nm CMOS技术中亚阈值操作的6T和10T SRAM单元的比较分析

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

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