Stacked die CSPs: Beyond chip size

摘要

Silicon efficiency is the ratio of the total area of ICs to the package area required to house them. The emergence of high-volume stacked die packaging applications began with thin small outline packages (TSOPs) and quad flat packages (QFPs) in the mid-1990s. By incorporating more than one die in these leadframe packages, significant improvements in silicon efficiency were achieved, approaching 100 percent.