The development of a complete complementary MESFET technology is presented. The state-of-the-art, fully implanted, CMOS-like process uses Shannon implants together with a refractory silicide Schottky-gate material to combine high gate barrier heights with ease of fabrication. To minimize parasitic resistances, a unique sidewall structure and sidewall spacers are utilized to allow for self-aligned implantation of the source/drain regions. A self-aligned titanium silicidation technique is employed to minimize sheet and contact resistance of the source/drain regions. The SUPREM process simulator was employed extensively. The performance and modeling of device parameters (e.g., threshold voltage, gate leakage, and short-channel effects) and circuit parameters (e.g. standby current, noise margin, and speed) were accomplished through analytic formulations, the PISCES two-dimensional device simulator, and the SPICE circuit simulator.
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