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首页> 外文期刊>IEEE Transactions on Electron Devices >Reduction of PN junction leakage current by using poly-Si interlayered SOI wafers
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Reduction of PN junction leakage current by using poly-Si interlayered SOI wafers

机译:使用多晶硅层间SOI晶片降低PN结泄漏电流

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摘要

A new type of silicon-on-insulator (SOI) structure was fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si, Si/sub 3/N/sub 4/, and SiO/sub 2/. The cross-sectional structures were analyzed by using SIMS, micro-Raman spectroscopy, and spreading resistance methods. Both the area components and the perimeter components of the PN-junction leakage current were reduced more than 10 fold in structures that had a poly-Si interlayer just beneath the active-devices to act as a gettering site. The leakage current was a function of tensile strength in the SOI layer and was easily controlled with a suitable combination of interlayered insulators.
机译:通过使用直接键合技术掩埋由多晶硅,Si / sub 3 / N / sub 4 /和SiO / sub 2 /组成的多层膜,制造了一种新型的绝缘体上硅(SOI)结构。通过使用SIMS,显微拉曼光谱和抗扩散性方法分析横截面结构。在有源器件下方具有多晶硅夹层的结构中,PN结泄漏电流的面积分量和周边分量都减少了10倍以上,从而起到了吸杂作用。漏电流是SOI层中抗拉强度的函数,并且可以通过适当的层间绝缘体组合轻松控制。

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