High-Voltage Power IC Technology With nVDMOS, RESURF pLDMOS, and Novel Level-Shift Circuit for PDF Scan-Driver IC

摘要

A novel high-voltage (HV) CMOS IC technology using 25-μm-thick epitaxy layer based on 1.2-μm standard CMOS process for color plasma display panel (PDP) scan-driver ICs has been developed. In this technology, HV n-channel vertical double diffused MOS (nVDMOS), reduced surface field p-channel lateral double diffused MOS (pLDMOS), and the low-voltage CMOS (LVCMOS) are integrated together. The p{sup}+n junction isolation is used to isolate nVDMOS from the pLDMOS, LVCMOS, and other nVDMOSs. A novel level-shift circuit has also been suggested in the PDP scan-driver IC. The experimental results show that the breakdown voltages of the presented nVDMOS and pLDMOS both exceed 200 V whether in the OFF or ON state. The rise and fall times of the proposed PDP scan-driver IC are about 270 and 50 ns, respectively, which are two important performances to the high response speed of PDPs. The power consumption of the proposed PDP scan-driver IC with the novel level shift circuit has been reduced by about 20% compared with that of the PDP scan-driver IC with the conventional level shift circuit. Furthermore, the cost can be greatly saved using the presented bulk-silicon fabrication technology compared with the silicon-on-insulator technology.