A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology

摘要

The holding voltage of the high-voltage devices the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause the high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used in the power-rail ESD clamp circuit. A new latchup-free design of the power-rail ESD clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35μm BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.