Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—DC Analysis and Modeling Toward Optimum Transistor Structure

摘要

Scaling of silicon technology continues while a research has started in other novel materials for future technology generations beyond year 2015. Carbon nanotubes (CNTs) with their excellent carrier mobility are a promising candidate. The authors investigated different CNT-based field effect transistors (CNFETs) for an optimal switch. Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs were systematically compared from a circuit/system design perspective. The authors have performed a dc analysis and determined how noise margin and voltage swing vary as a function of tube diameter and power-supply voltage. The dc analysis of single-tube SB CNFET transistors revealed that the optimum CNT diameter for achieving the best ION-to-IOFF ratio while maintaining a good noise margin is about 1 to 1.5 nm. Despite several serious technological barriers and challenges, CNTs show a potential for future high-performance devices as they are being researched