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Feasibility Study of 45-nm-Node Scaled-Down Cu Interconnects With Molecular-Pore-Stacking (MPS) SiOCH Films

机译:45纳米节点按比例缩小的铜互连与分子孔堆叠(MPS)SiOCH膜的可行性研究

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摘要

A feasibility study was done for 45-nm-node Cu interconnects using a novel molecular-pore-stacking (MPS) SiOCH film (k = 2.45), taking electron scattering in the scaled-down Cu lines into consideration. The as-deposited MPS SiOCH film, formed by plasma polymerization of a robust six-member-ring (hexagonal) siloxane with large steric-hindered hydrocarbon side chains, has self-organized subnanometer pores. An oxidation-damage-free dual-hard-mask etching process, along with a benzocylobuten liner technique, preserved the low permittivity of the MPS film in the Cu lines, with excellent interline dielectric reliability. The line aspect ratio was also balanced to decrease not only the interconnect parasitic capacitance but also the Cu line resistivity, which is increased by the electron scattering in the narrow lines. By combining the above etching process and the line-aspect control, the feasibility of the MPS SiOCH film was confirmed with outstanding performance and excellent reliability for the 45-nm-node ultralarge scale integrations
机译:考虑到按比例缩小的Cu线中的电子散射,使用新型分子孔堆叠(MPS)SiOCH膜(k = 2.45)对45 nm节点的Cu互连进行了可行性研究。沉积后的MPS SiOCH膜由具有大的位阻烃侧链的坚固的六元环(六边形)硅氧烷通过等离子体聚合形成,具有自组织的亚纳米孔。无氧化损伤的双硬掩模蚀刻工艺,加上苯并氯丁烯衬里技术,保持了MPS膜在Cu线中的低介电常数,并具有出色的线间介电可靠性。线宽比也得到了平衡,不仅减小了互连寄生电容,而且减小了铜线的电阻率,而铜线的电阻率由于窄线中的电子散射而增加。通过将上述蚀刻工艺和线宽控制相结合,证实了MPS SiOCH膜具有出色的性能和出色的可靠性,可用于45纳米节点的超大规模集成。

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