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Improvement of Uniformity and Reliability of Scaled-Down Cu Interconnects with Carbon-Rich Low-k Films

机译:富碳低k薄膜的按比例缩小铜互连的均匀性和可靠性的改善

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摘要

Highly selective dry-etching processes are developed for conventional via-first (VF) pattering sequences to fabricate reliable Cu dual-damascene interconnects (DDI) in carbon-rich low-k films, such as a molecular-pore-stack (MPS) SiOCH film (k = 2.55). The carbon-rich MPS film, which had excellent endurance against plasma-processes, acted as etching stopper during hard-mask (HM)-etching on it, and the high selectivity of trench-HM etching reduced variability of over-etching depth in the MPS film. This effect reduced variability in trench-depth in the MPS film, or interconnect characteristics such as capacitance-resistance (C-R) time delay. The via yield and reliability were influenced also by via-etch selectivity of MPS against SiCN cap underlain. We found that the SiCN thickness remained after the via etch should be greater than 10nm to prevent Cu from oxidation by O_2 ashing step followed. Chemical-reaction-enhanced gas chemistry in N_2-CFx-Ar system, i.e., high N_2/Ar ratio under limited CF_x supply, increased the etching selectivity of MPS to keep enough thickness of SiCN. Early-failure-mode in electro-migration test was suppressed by the high selective via-etch. Precise selectivity control for robust carbon-rich low-k films was very important to achieve the low variability and high reliability of scaled-down Cu interconnects.
机译:针对常规的先通孔(VF)图案化工艺开发了高度选择性的干法蚀刻工艺,以在富含碳的低k膜(例如分子孔堆叠(MPS)SiOCH)中制造可靠的铜双大马士革互连(DDI)胶卷(k = 2.55)。富含碳的MPS膜具有出色的抗等离子体处理能力,可在其上进行硬掩模(HM)刻蚀时用作刻蚀停止层,而沟槽HM刻蚀的高选择性降低了刻蚀深度的可变性。 MPS胶卷。这种效果减少了MPS膜中沟槽深度的变化或互连特性(例如,电容电阻(C-R)时间延迟)。通孔产量和可靠性还受到MPS对SiCN盖衬底的通孔蚀刻选择性的影响。我们发现,通孔蚀刻后保留的SiCN厚度应大于10nm,以防止Cu被随后的O_2灰化步骤氧化。 N_2-CFx-Ar系统中的化学反应增强了气体化学性质,即在CF_x供给受限的情况下具有较高的N_2 / Ar比,从而提高了MPS的蚀刻选择性以保持足够的SiCN厚度。高迁移率通孔蚀刻抑制了电迁移测试中的早期失效模式。鲁棒的富含碳的低k薄膜的精确选择性控制对于实现按比例缩小的Cu互连的低可变性和高可靠性非常重要。

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  • 来源
    《Japanese journal of applied physics》 |2011年第4issue2期|p.04DB02.1-04DB02.5|共5页
  • 作者单位

    LSI Research Laboratory, Renesas Electronics Corporation, 1120 Shimokuzawa, Chuo-ku, Sagamihara 252-5298, Japan;

    LSI Research Laboratory, Renesas Electronics Corporation, 1120 Shimokuzawa, Chuo-ku, Sagamihara 252-5298, Japan;

    LSI Research Laboratory, Renesas Electronics Corporation, 1120 Shimokuzawa, Chuo-ku, Sagamihara 252-5298, Japan;

    LSI Research Laboratory, Renesas Electronics Corporation, 1120 Shimokuzawa, Chuo-ku, Sagamihara 252-5298, Japan;

    LSI Research Laboratory, Renesas Electronics Corporation, 1120 Shimokuzawa, Chuo-ku, Sagamihara 252-5298, Japan;

    LSI Research Laboratory, Renesas Electronics Corporation, 1120 Shimokuzawa, Chuo-ku, Sagamihara 252-5298, Japan;

    LSI Research Laboratory, Renesas Electronics Corporation, 1120 Shimokuzawa, Chuo-ku, Sagamihara 252-5298, Japan;

    LSI Research Laboratory, Renesas Electronics Corporation, 1120 Shimokuzawa, Chuo-ku, Sagamihara 252-5298, Japan;

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