Precise Taper-Angle-Control of Via Holes for Reliable Scaled-Down Low-k/Cu Interconnects

摘要

A highly reliable Cu dual-damascene interconnect (DDI) was developed in a molecular-pore-stack (MPS) SiOCH film (k = 2.5) with precise taper angle control at the top and bottom of via holes. The durable MPS film with the carbon-rich composition revealed no reliability deterioration in the time-dependent dielectric breakdown (TDDB) between the 140-nm pitched lines. The stres-induced voiding (SiV) was suppressed completely by precise taper angle control both at the top and bottom of via holes. A shallow-tapered via and a stepped via, in which these top taper angles (θ_(top)) were greater than 45° while keeping the bottom angle (θ_(btm)) steep at approximately 90°, improved the SiV reliability referred to a deep-tapered via with θ_(btm) 90°. Finite element method (FEM) simulation well explalns the dependence of SiV reliability on both θ_(top) and θ_(btm); the increment of θ_(top) reduces the stress gradient under the via, while the decrease in θ_(btm) enlarges the stress gradient. Namely, the precise taper angle control of both the top and bottom via is very important to improve the SiV reliability, and the shallow-tapered and the stepped vias in the MPS film were confirmed to achieve high endurance agalnst the SiV due to relaxation of the stress gradient under the via.