首页> 外文期刊>IEEE Transactions on Electron Devices >Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD $hbox{HfO}_{2}$ Gate Dielectric and Si Surface Passivation
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Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD $hbox{HfO}_{2}$ Gate Dielectric and Si Surface Passivation

机译:使用CVD $ hbox {HfO} _ {2} $栅极介电和Si表面钝化的自对准栅优先Ge p和n沟道MOSFET的特性

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The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO2 as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO2 gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO2/Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO2 /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication
机译:广泛研究了在锗上制造的p-和n-MOS器件的电学性质,该金属有机化学气相沉积HfO2作为栅极电介质,硅钝化(SP)作为表面处理。高K沉积之前的表面处理对于实现较小的栅极泄漏电流以及较小的等效氧化物厚度至关重要。与表面氮化处理相比,SP提供了改进的界面质量,特别是对于p型衬底上的栅叠层。 SP演示了具有HfO2栅极电介质的Ge p和n-MOSFET。在高电场(〜0.6 MV / cm)下,测得的空穴迁移率比通用SiO2 / Si系统的空穴迁移率高82%,并且与CVD HfO2 / Si相比,Ge n沟道MOSFET的峰值电子迁移率提高了约61%。系统实现了。最后,与硅控制器件相比,Ge MOSFET的偏置温度不稳定性(BTI)降低得到了表征。由于价带偏移较大,因此在Ge SP p-MOSFET中观察到的负BTI退化比硅控制器件少,而在Ge SP n-MOSFET中,与硅控制相比,BSP的正BTI正退化大,其原因可能是低器件制造过程中的加工温度

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