The amount of FN-disturb-induced erase-level shift in a sub-90-nm-node embedded polysilicon/oxideitride/oxide/silicon-type trap memory was found to peak at 25 $^{circ}hbox{C}$ to decrease briefly at 90 $^{circ}hbox{C}$ and then to increase again at higher temperatures. This characteristic temperature dependence can be explained by three processes. First, electrons are injected from the substrate into the nitride layer through traps in the bottom oxide $(B_{rm ox})$. Second, holes that are trapped in the $B_{rm ox}$ during program/erase cycles increase the electric field in the $B_{rm ox}$ near the substrate, thus enhancing the effect of the electron injection. Third, this enhancement is weaker at elevated temperatures because of hole emission from the $B_{rm ox}$. We propose empirical fitting equations for describing the FN-disturb behavior, which consider the effects of traps and holes within the $B_{rm ox}$. Moreover, we show that the effect of nitriding the $B_{rm ox}$ layer on FN-disturb immunity results from a decrease in the trap density of the $B_{rm ox}$.
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