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Contact-Resistance Reduction for Strained n-FinFETs With Silicon–Carbon Source/Drain and Platinum-Based Silicide Contacts Featuring Tellurium Implantation and Segregation

机译:具有碲离子注入和隔离的硅碳源/漏和铂基硅化物触点可降低应变n-FinFET的接触电阻

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摘要

Tellurium (Te) implantation was introduced to tune the effective electron Schottky barrier height (SBH) $Phi_{B}^{n}$ of platinum-based silicide (PtSi) contacts formed on n-type silicon–carbon (Si:C). Te introduced by ion implantation prior to Pt deposition segregated at the PtSi:C/Si:C interface during PtSi:C formation. The presence of Te at the PtSi:C/Si:C interface leads to a low $Phi_{B}^{n}$ of 120 meV for PtSi:C contacts. The integration of Te-segregated PtSi:C contacts on strained n-channel fin field-effect transistors (FinFETs) with Si:C source/drain (S/D) stressors achieves the lowering of the parasitic series resistance $R_{SD}$ by $sim$62% and increases the saturation drive current by $sim$22%. The Te-segregated contact-resistance reduction technology does not degrade the short-channel effects and positive-bias temperature instability characteristics of n-FinFETs with Si:C S/D. As PtSi has a low SBH for holes and is a suitable contact for p-FinFETs, this new contact-resistance reduction technology has potential to be introduced as a single-metal-silicide dual-barrier-height solution for future complementary metal–oxide–semiconductor FinFET technology.
机译:引入碲(Te)注入是为了调整在n型硅碳(Si:C)上形成的铂基硅化物(PtSi)触点的有效电子肖特基势垒高度(SBH)$ Phi_ {B} ^ {n} $ 。在PtSi:C形成过程中,在Pt沉积之前通过离子注入引入的Te在PtSi:C / Si:C界面处偏析。 Te在PtSi:C / Si:C界面处的存在会导致PtSi:C触点的$ Phi_ {B} ^ {n} $低至120 meV。 Te隔离的PtSi:C触点在应变n沟道鳍式场效应晶体管(FinFET)上与Si:C源/漏(S / D)应力源的集成实现了寄生串联电阻$ R_ {SD} $的降低增加$ sim $ 62%,并使饱和驱动电流增加$ sim $ 22%。 Te隔离的接触电阻降低技术不会降低具有Si:C S / D的n-FinFET的短沟道效应和正偏置温度不稳定性。由于PtSi的孔SBH较低,并且是p-FinFET的合适触点,因此这种新的降低接触电阻的技术有可能被引入作为单金属硅化物双势垒高度解决方案,以用于将来的互补金属氧化物半导体FinFET技术。

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