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Capacitance Modeling and Characterization of Planar MOSCAP Devices for Wideband-Gap Semiconductors With High-$kappa$ Dielectrics

机译:用于具有高介电常数的宽带隙半导体的平面MOSCAP器件的电容建模和特性表征

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摘要

This paper presents a capacitance model and mobility extraction method through the use of tapered transmission line theory for accumulation-mode MOSCAP test structures. The analytical model accounts for the discrepancies commonly found when measuring the capacitance of nontraditional MOSCAP architectures. Through fabrication of a planar MOSCAP, this model accurately reproduced consistent capacitance density measurements for several device dimensions and high-$kappa$ dielectric thicknesses. In this paper, the theoretical basis of the model extracts the effective electron mobility of the accumulation channel in the semiconductor without fabricating a transistor.
机译:本文通过使用锥形传输线理论对累积模式MOSCAP测试结构提出了一种电容模型和迁移率提取方法。分析模型解决了在测量非传统MOSCAP架构的电容时通常发现的差异。通过制造平面MOSCAP,该模型可精确再现出针对多个器件尺寸和高介电常数厚度的一致电容密度测量结果。在本文中,该模型的理论基础可在不制造晶体管的情况下提取半导体中累积沟道的有效电子迁移率。

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